The semiconductor industry continues to make smaller and smaller integrated circuits. This reduction in size of an integrated circuit is in part due to smaller lithographies. Accordingly, devices made from smaller lithographies are scaled down as well. With respect to a transistor, gate insulator thickness (“gate oxide” or more accurately “gate dielectric”) has become thinner as devices have become smaller.
A thin gate dielectric conventionally is not as insulative as a thicker gate dielectric because of electron tunneling across the dielectric. In order to prevent tunneling currents from negatively impacting transistor operation, materials other than silicon oxide have evolved for use as transistor gate dielectrics including, but not limited to, nitrides such as silicon nitride. Moreover, substantial effort has been made to create high quality dielectrics for thin gate insulators. By thin gate insulator is meant an oxide or other dielectric having a thickness of less than approximately 20 Angstroms. Such a thin gate insulator is conventionally formed using a process having a lithographic minimum dimension of about 0.1 microns (100 nanometers) or less. But forming an oxide or other dielectric that is 20 Angstroms or less in thickness is problematic. Thus, MOSFETs (metal-oxide-semiconductor-field-effect-transistors) may comprise a combination of materials, such as layering of silicon nitride and silicon dioxide in order to form a gate that is as thin as possible but which limits tunneling current.
Power supply independent current reference circuits conventionally use components with differing current-voltage (I-V) characteristics in conjunction with a current mirror circuit and other components to generate reference current or currents which are a weak function of a power supply voltage. Alternatively, voltages may be similarly generated in, for example, voltage proportional to absolute temperature (PTAT) circuits and bandgap generation circuits that conventionally use two or more bipolar junction transistors (BJTs).
A problem faced by the semiconductor industry is that MOSFET-only self-biasing circuits, such as a threshold reference self-biasing circuit, generate voltages that tend to vary from wafer to wafer and may also vary over time. Moreover, MOSFET-only self-biasing circuits may substantially drift with temperature. Accordingly, such high sensitivity to process variability and temperature drift makes MOSFET-only self-biasing circuits problematic.
Self-biasing circuits formed with one or more BJTs are conventionally formed using bipolar and metal-oxide-semiconductor (MOS) processes. Contemporary MOS processes combine P and N type MOS devices on what is commonly known as a CMOS or complementary MOS process. These CMOS processes usually allow parasitic BJT transistors to be fabricated along with P and N type MOSFETs without requiring additional process steps. However, as supply voltages are reduced, BJTs are more difficult to use with CMOS circuits. In order to maintain reliable performance, contemporary MOS circuits with lithographic dimensions on the order of 100 nm have reduced supply voltage, Vdd, to approximately one volt. Conventional silicon BJTs require a forward base-emitter voltage of approximately 0.7 volts. Thus, there is limited margin for operation of such BJTs with low voltage MOS circuits. Moreover, the parasitic BJTS that are easily available on advanced CMOS processes usually exhibit very low current gain, on the order of one. This very low current gain can lead to poor reference performance with conventional design strategies.
Accordingly, it would be desirable and useful to provide a self-biasing circuit formed with only MOSFETs that is less susceptible to process variation and temperature.